IBIS Macromodel Task Group

Meeting date: 11 March 2014

Members (asterisk for those attending):
Agilent:                    * Fangyi Rao
                            * Radek Biernacki
Altera:                     * David Banas
ANSYS:                      * Dan Dvorscak
                            * Curtis Clark
Cadence Design Systems:     * Ambrish Varma
                              Brad Brim
                            * Kumar Keshavan
                            * Ken Willis
			    * Scott Huss
Ericsson:                     Anders Ekholm
Intel:                      * Michael Mirmak
Maxim Integrated Products:    Hassan Rafat
Mentor Graphics:            * John Angulo
                            * Arpad Muranyi
			    * Andrey Matvienko
Micron Technology:            Randy Wolff
                            * Justin Butterfield
QLogic Corp.                  James Zhou
                              Andy Joy
SiSoft:                     * Walter Katz
                              Todd Westerhoff
                            * Mike LaBonte
Teraspeed Consulting Group:   Scott McMorrow
                            * Bob Ross

The meeting was led by Arpad Muranyi

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Opens:

- Michael M: The informal group working on package proposals believes it would
  be best to convene a formal task group.
  - Those interested should suggest available times.
- Arpad: We used to meet Wednesday mornings.


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Call for patent disclosure:

- None

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Review of ARs:

- Mike L. needs to upload versions of BIRD 147.
  - Need to find an email that has the attachment.

- Subcommittee will work on more package proposals.
  - Walter: These ARs should be moved to the new packaging task group.

- Bob and Ambrish - BIRD 147 editorial work.
  - Ongoing.

- Arpad to make a BIRD163 syntax version of Walter's example.
  - Done.

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New Discussion:

Introduction of Scott Huss:
- System architecture and interface design at Cadence in Cary, NC.

Back-channel discussion:
- Scott Huss showed a presentation "Back Channel Adaptive Transmit Equalization".
- slide 3:
  - Scott: DFE is always in the RX, FFE can be in TX or RX.
- slide 4:
  - Scott: Need an ADC for FFE/DFE in RX.
- slide 5:
  - Scott: Measurement facilities are needed for back-channel operation.
    - Instructions are sent back to the TX.
- slide 6:
  - Scott: The RX requires 5 or 6 bit ADCs.
    - There have been analog implementations, but they are rare.
    - A specific protocol is required for the back-channel.
- slide 7:
  - Scott: Fixed programmable TX FFEs in slower standards are hard to work with.
    - PCIe3 protocol uses LF and FS.
    - LF = Low Frequency.
    - FS = Full Scale.
- slide 8:
  - Scott: The PIPE standard uses a figure of merit.
    - This is used by an adaptive search algorithm.
    - An LMS algorithm can control both RX DFE and TX FFE.
- slide 10:
  - Scott: This table shows 9 presets for a typical PCIe3 convergence scheme.
    - TX devices usually have some presets.
    - In this case preset P7 happens to be almost as good as adaptive mode.
  - Michael M: Aren't the recommended presets a known starting point?
    - Without starting at a known point local maxima and minima might be found.
  - Scott: Usually a good convergence is found regardless of starting preset.
  - Fangyi: Did the Adapt settings start at some preset?
  - Scott: I started from P4 for that run.
  - Fangyi: What do the pre and post columns mean?
  - Scott: Those are codes for chosen values.
  - Fangyi: Is this in a standard?
  - Scott: The PCIe3 standard has parts of this.
    - 10Gkr is similar but gives more freedom.
  - Bob: What is Pre-Shoot?
  - Scott: pre-cursor in dB.
  - Fangyi: Does the cursor sign matter?
  - Scott: The coefficients have to always be negative, not sure why.
- slide 12:
  - Scott: This shows convergence over time graphically.
- slide 13:
  - Scott: Sometimes the DFE is filtered, sometimes not.
    - This has two eyes combined together.
- slide 14, 15, 16:
  - Scott: These show improving eyes.
- slide 12:
  - Fangyi: Are these for different channels?
  - Scott: It is the same channel.
    - The multiple curves are for different starting presets.
  - David: Is this showing different elements of the receiver?
  - Scott: Yes.
- slide 17:
  - Scott: For another experiment adaption had to be handled manually.
    - In a real system the whole protocol stack would be there.
    - Jitter is factored in for this test.
- slide 18:
  - Scott: The preset chosen doesn't affect jitter tolerance much.
  - David: Why is P7 not one of the best, considering it started off so well?
  - Scott: Different channels may have been used.
- slide 19: Conclusion

- Michael M: Are you looking for very specific protocol handling or something more abstract.
- Scott: Abstract would be good.

- Walter: Two questions must be asked:
  - What will the optimum setting be?
  - Will the SerDes find it?
  - There are two approaches.
- Scott: There is not a strong need to find optimum settings.
- Michael M: One answer is "both".
  - We might assume any optimization will be in the model.
  - Or the model might suggest settings that the buffer can't even implement.
  - System designers might like that.
- David: Is that a warning of sorts?
- Michael M: The algorithms can be valuable, but they should be non-silicon based models.
  - This is a good thing, but dangerous.
  - The final answer depends on the algorithm.
- Fangyi: How frequent are the back-channel updates?
- Scott: It is only at startup, with a timeout.
  - Other than that there is no limit.
- Kumar: It is not a significant simulator load.
- Fangyi: The concern would be about block size.

Arpad:  We will look at memory_package_1p3.ibs, an IBIS example:

Michael M: Please let me know if you wish to participate in packaging discussions.
- Also please suggest meeting times.

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Next meeting: 18 March 2014 12:00pm PT

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IBIS Interconnect SPICE Wish List:

1) Simulator directives